Papers

  • S. Uhlich, A. Bonetti, A. Venkitaramanm, A. Momeni, R. Matsuo, C. Hsieh, E. Ohbuchi, L. Servadei, “GraCo - A Graph Composer for Integrated Circuits”. arXiv 2024.
  • R. Matsuo, S. Uhlich, A. Venkitaraman, A. Bonetti, C. Hsieh, A. Momeni, L. Mauch, A. Capone, E. Ohbuchi, L. Servadei, “Schemato - An LLM for Netlist-to-Schematic Conversion”. arXiv 2024.
  • P. Jokic, E. Azarkhish, A. Bonetti, M. Pons, S. Emery, and L. Benini, “A Construction Kit for Efficient Low Power Neural Network Accelerator Designs”. ACM TECS 2022.
  • E. M. Calvo, P. Renevey, M. Lemay, A. Bonetti, M. Pons Solé, R. Cattenoz, S. Eméry, and R. Delgado-Gonzalo, “Ultra-low-power Physical Activity Classifier for Wearables: From Generic MCUs to ASICs”. IEEE EMBC 2021.
  • A. Bonetti, R. Golman, R. Giterman, A. Teman, and A. Burg, “Gain-Cell Embedded DRAMs: Modeling and Design Space”. IEEE TVLSI 2020.
  • R. Giterman, A. Bonetti, E. V. Bravo, T. Noy, A. Teman, and A Burg, “Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space”. IEEE TCAS-I 2020.
  • R. Giterman, A. Bonetti, A. Burg, and A. Teman, “GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI”. IEEE TCAS-II, January 2019.
  • B. W. Denkinger, F. Ponzina, S. S. Basu, A. Bonetti, S. Balási, M. Ruggiero, M. Peón-Quirós, D. Rossi, A. Burg, and D. Atienza, “Impact of memory voltage scaling on accuracy and resilience of deep learning based edge devices”. IEEE Design & Test 2019.
  • J. Narinx, R. Giterman, A. Bonetti, N. Frigerio, C. Aprile, A. Burg, and Y. Leblebici, “A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications”. IEEE ASSCC 2019.
  • M. Widmer, A. Bonetti, and A. Burg, “FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing Systems “. Design Automation Conference (DAC) 2019.
  • Ester Vicario Bravo, A. Bonetti, and A. Burg, “Data-Retention-Time Characterization of Gain-Cell eDRAMs across the Design and Variations Space”. IEEE ISCAS 2019.
  • A. Bonetti, J. Constantin, A. Teman, and A. Burg, “A Timing-Monitoring Sequential for Forward and Backward Error-Detection in 28 nm FD-SOI”. IEEE ISCAS 2018.
  • A. Bonetti, A. Teman, P. Flatresse, and A. Burg, “Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters”. IEEE TCAS-I 2017.
  • A. Bonetti, N. Preyss, A. Teman, and A. Burg, “Automated Integration of Dual-Edge Clocking for Low- Power Operation in Nanometer Nodes”. ACM TODAES, May 2017.
  • P. Giard, A. Balatsoukas-Stimming, T. C. Müller, A. Bonetti, C. Thibeault, W. J. Gross, P. Flatresse, and A. Burg, “PolarBear: A 28nm FD-SOI ASIC for Decoding of Polar Codes”. IEEE JETCAS 2017.
  • S. Brenna, A. Bonetti, A. Bonfanti, and A. Lacaita, “An Efficient Tool for the Assisted Design of SAR ADCs Capacitive DACs”. Integration, the VLSI Journal, Elsevier 2016.
  • J. Constantin, A. Bonetti, A. Teman, Christoph Müller, Lorenz Schmid, and A. Burg, “DynOR: A 32-bit Microprocessor in 28nm FD-SOI with Cycle-By-Cycle Dynamic Clock Adjustment”. IEEE ESSCIRC 2016.
  • S. Brenna, L. Bettini, A. Bonetti, A. Bonfanti, and A. Lacaita, “Fundamental Power Limits of SAR and ∆Σ Analog-to-Digital Converters”. IEEE NORCAS 2015.
  • A. Bonetti, A. Teman, and A. Burg, “An Overlap-Contention Free True-Single-Phase Clock Dual-Edge- Triggered Flip-Flop”. IEEE ISCAS 2015.
  • P. Meinerzhagen, A. Bonetti, G. Karakonstantis, C. Roth, F. Gürkaynak, and A. Burg, “Refresh-Free Dynamic Standard-Cell Based Memories: Application to a QC-LDPC Decoder”. IEEE ISCAS 2015.
  • S. Brenna, A. Bonetti, A. Bonfanti, and A. Lacaita, “A Tool for the Assisted Design of Charge Redistribution SAR ADCs”. DATE 2015.
  • S. Brenna, A. Bonetti, A. Bonfanti, and A. Lacaita. “A Simulation and Modeling Environment for the Analysis and Design of Charge Redistribution DACs used in SAR ADCs”. IEEE MIPRO 2014.

Patents

  • A. Bonetti, J. P. Kulkarni, C. Tokunaga, M. Cho, P. A. Meinerzhagen, and M. M. Khellah, “Voltage Level Shifter Monitor with Tunable Voltage Level Shifter Replica Circuit”. U.S. Patent Application No. 10,243,563 issued on March 26, 2019.

Talks

  • A. Teman, A. Bonetti, C. Müller, and A. Burg, “FD-SOI Standard Cell Characterization with Cadence Liberate”. Cadence User Conference (CDNlive) Israel, November 2016 (Best Paper Award).
  • A. Bonetti, N. Preyss, A. Teman, and A. Burg, “Automated Integration of Dual-Edge Triggered Clocking into the Standard Design Flow”. Cadence User Conference (CDNlive) EMEA, April 2015.